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Description:
Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).
reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.
The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.
module top_module( input clk, input reset, input ena, output pm, output [7:0] hh, output [7:0] mm, output [7:0] ss); always@(posedge clk)begin if(reset|(ena&&ss[7:0]==8'h59)) ss<=8'h00; else begin if(ena&&ss[3:0]==4'h9) ss[3:0]<=0; else begin if(ena) ss[3:0]<=ss[3:0]+1; else ss[3:0]<=ss[3:0]; end if(ena&&ss[3:0]==4'h9) ss[7:4]<=ss[7:4]+1; else ss[7:4]<=ss[7:4]; end end //秒 always@(posedge clk)begin if(reset|(ena&&mm==8'h59&&ss==8'h59)) mm[7:0]<=8'h00; else begin if(ena&&ss[7:0]==8'h59) mm[3:0]<=mm[3:0]+1; if(ena&&mm[3:0]==4'h9&&ss[7:0]==8'h59)begin mm[7:4]<=mm[7:4]+1; mm[3:0]<=0; end end end //分钟 always@(posedge clk)begin if(reset)begin hh[7:0]<=8'h12; pm<=0; end else begin if(ena&&hh[7:0]==8'h11&&mm[7:0]==8'h59&&ss[7:0]==8'h59)begin pm<=~pm; hh[7:0]<=8'h12; end if(ena&&ss[7:0]==8'h59&&mm[7:0]==8'h59)begin if(hh[7:0]==8'h12) hh[7:0]<=8'h01; else if(hh[3:0]==4'h9)begin hh[7:4]<=hh[7:4]+1; hh[3:0]<=4'h00; end else hh[3:0]<=hh[3:0]+1; end end end endmodule
(初学Verilog,如果有大佬看见欢迎指教)
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